1. Field of the Invention
The present invention relates to a clock driver circuit for use in a semiconductor device, and more specifically to a clock driver circuit for generating a non-inverted clock signal and an inverted clock signal which have a reduced phase deviation to each other.
2. Description of Related Art
A clock driver circuit for use in a semiconductor device is generally used to distribute a basic clock generated in a clock generator internally provided in the semiconductor device or supplied from an external, to various internal circuits of the semiconductor device.
Referring to FIG. 1, there is shown a circuit diagram of the most general circuit of the clock driver circuit. The shown clock driver circuit includes a pair of inverters 34 and 35 having a high driving power, cascaded between an input terminal 1 and a non-inverted signal output terminal 3. The shown clock driver circuit also includes an inverter 36 connected between the input terminal 1 and an inverted signal output terminal 2.
If a clock signal is supplied through the input terminal 1 to each input of the inverters 34 and 36, a non-inverted clock signal is outputted from an output of the inverter 35 to the non-inverted signal output terminal 3, and an inverted clock signal is outputted from an output of the inverter 36 to the inverted signal output terminal 2.
Japan Society of Electronics, Information and Communication, Spring Meeting Transactions, 1992, C-565, Page 186 discloses another prior art. Referring to FIG. 5 showing a clock driver circuit disclosed in this paper, an even number of inverters 37, 38, 39 and 40 are cascaded between the input terminal 1 and the non-inverted signal output terminal 3, and an even number of inverters 41 and 42 are cascaded between an output of the inverter 37 and the inverted signal output terminal 2. Transistors of the inverters 38 and 39 are designed to have a size larger than that of transistors of the other inverters 37, 40, 41 and 42.
In this example, when a clock signal is applied through the input terminal 1 to an input of the inverter 37, a non-inverted clock signal is outputted from an output of the inverter 40 to the non-inverted signal output terminal 3, and an inverted clock signal is outputted from an output of the inverter 42 to the inverted signal output terminal 2.
Since the non-inverted clock signal is outputted by passing through the four inverter stages 37, 38, 39 and 40, the non-inverted clock signal is delayed in phase from the inverted clock signal outputted by passing through the three inverter stages 37, 41 and 42. However, since the transistor size of the inverters 38 and 39 are designed to be larger than those of the other inverters 37, 40, 41 and 42, the inverters 38 and 39 has a faster switching speed, and therefore, it is possible to obtain the non-inverted clock signal substantially in the same phase as the inverted clock signal.
Japanese Patent Application Laid-open Publication No. JP-A-127814 discloses still another prior art. Referring to FIG. 6 showing a clock driver circuit disclosed in this Japanese patent laid-open publication (partially replaced by a logic gate), a pair of inverters 43 and 44 are cascaded between the input terminal 1 and the non-inverted signal output terminal 3.
On the other hand, an inverted signal generating circuit includes a source follower circuit composed of P-channel insulated gate field effect transistors (called "P-channel MOS transistors" hereinafter) 45 and 46, another source follower circuit composed of N-channel insulated gate field effect transistors (called "N-channel MOS transistors" hereinafter) 47 and 48, and an inverter circuit composed of a P-channel MOS transistor 49 and an N-channel MOS transistor 50. A gate of each of the P-channel MOS transistor 46 and the N-channel MOS transistor 47 is connected to the input terminal 1, and a gate of each of the P-channel MOS transistor 45 and the N-channel MOS transistor 48 is connected to an output of the inverter 43. A source of the P-channel MOS transistor 46 is connected to a gate of the P-channel MOS transistor 49, and a source of the N-channel MOS transistor 47 is connected to a gate of the N-channel MOS transistor 50. Thus, an inverted signal is outputted to the inverted signal output terminal 2 from an output of the inverter circuit composed of the P-channel MOS transistor 49 and the N-channel MOS transistor 50.
Referring to FIG. 2 showing a timing chart illustrating an operation of the conventional clock driver shown in FIG. 1, since two inverter stages are inserted between the input terminal 1 and the non-inverted signal output terminal 3 and on the other hand only one inverter stage is inserted between the input terminal 1 and the inverted signal output terminal 2, the non-inverted output clock signal 3 is delayed from the inverted output clock signal 2 by T6 which corresponds to a delay of one inverter stage. Therefore, when the clock driver circuit is caused to operate at a high speed, it is not possible to obtain a non-inverted clock signal and an inverted clock signal in phase to each other.
Referring to FIG. 3 showing an operation waveform of the conventional clock driver circuit, when a pulse having a frequency of 200 MHz as shown in a lower half of FIG. 3 was applied, a non-inverted clock signal 3 and an inverted clock signal 2 were obtained as shown in an upper half of FIG. 3. It will be noted that, when the input pulse is 200 MHz, the non-inverted clock signal 3 and the inverted clock signal 2 should be properly deviated from each other precisely 2.5 ns, but are actually deviated from each other about 2 ns at a minimum and about 3 ns at maximum.
Here, examine a case that the non-inverted clock signal and the inverted clock signal obtained in the clock driver circuit shown in FIG. 1 are supplied to a master-slave T-type flipflop as a clock.
FIG. 4 shows a circuit diagram of a typical master-slave T-type flipflop. This master-slave T-type flipflop includes a master flipflop comprising a transfer gate 51, inverters 52 and 53 and another transfer gate 53 cascaded as shown with an output of the transfer gate 53 being connected to an input of the inverter 52 so as to form a latch circuit. The transfer gate 51 is controlled to be turned on when a clock C corresponding to the above mentioned non-inverted clock signal is at a low level, and an inverted clock C corresponding to the above mentioned inverted clock signal is at a high level. The transfer gate 54 is controlled to be turned on when the clock C is at a high level and the inverted clock C is at a low level.
The master-slave T-type flipflop also includes a slave flipflop comprising a transfer gate 55, inverters 56 and 57 and another transfer gate 58 cascaded as shown with an output of the transfer gate 58 being connected to an input of the inverter 56 so as to form a latch circuit. The transfer gate 55 is controlled to be turned on when the clock C is at a high level and the inverted clock C is at a low level. The transfer gate 58 is controlled to be turned on when the clock C is at a low level and the inverted clock C is at a high level. An output of the inverter 52, which constitutes an output of the master flipflop, is connected to an input of the transfer gate 55 of the slave flipflop, and an output of the inverter 56, which constitutes an output of the slave flipflop, is connected to an output terminal 60 and also connected through an inverter 59 to an input of the transfer gate 51 of the master flipflop.
When the transfer gate 51 is conductive and the transfer gate 54 is non-conductive, the master flipflop is put into a condition capable of receiving an input signal. At this time, the transfer gate 51 is brought into a conductive condition having a small on-resistance, basically when the clock C is at a low level and the inverted clock C is at a high level. However, at least if the inverted clock C is at a high level or if the clock C is at a low level, the transfer gate 51 can allow passage of the signal with about a double on-resistance. Accordingly, the period T2 in FIG. 2 corresponds to a period of capable of receiving the input signal. Similarly, at least if the inverted clock C is at a low level or if the clock C is at high level, the transfer gate 54 becomes a conductive condition and can allow passage of the signal. This period corresponds to the period T1 in FIG. 2.
Accordingly, a period in which the master flipflop is put in a hold condition corresponds to the period T3 in FIG. 2 in which the transfer gate 51 is in the non-conductive condition and the transfer gate 54 is in the conductive condition. During the period T4, the transfer gate 51 is conductive and the transfer gate 54 is non-conductive, so that the master flipflop is in the latching or data receiving condition.
During the period T5 generated by the phase difference between the clock C and the inverted clock C, both the clock C and the inverted clock C are at a high level, and during the period T6 also generated by the phase difference between the clock C and the inverted clock C, both the clock C and the inverted clock C are at a low level. Accordingly, both the master flipflop and the slave flipflop are put into the condition capable of receiving the data signal and allowing passage of the data signal. In this condition, the outputs of the inverters 59 and 53 conflict, and the outputs of the inverters 52 and 57 conflict. This is a cause for malfunction.
In addition, the periods T3 and T4 become shorter than a half of one period of the input clock. In other words, since the non-inverted signal and the inverted signal overlap each other during the periods T5 and T6, the flipflop must operate at a frequency apparently higher than the frequency of the input signal, and therefore, it is happens that the frequency of the input signal must be made low.
On the other hand, in order to overcome the above mentioned defect and to make the non-inverted signal and the inverted signal completely complementary to each other, the conventional clock driver circuit shown in FIG. 5 is configured to have the large size inverters in the path composed of a large number of stages for the non-inverted output signal and the small size inverters in the path composed of a small number of stages for the inverted output signal, for the purpose of cancelling the phase difference between the non-inverted output signal and the inverted output signal.
For example, assuming that next stage inverters connected to the non-inverted signal output terminal 3 and the inverted signal output terminal 2 have a size of "1", the sizes of the inverters 38, 39, 40, 41 and 42 are made "8", "4", "2", "0.37" and "0.61", respectively. If this relation is normalized by putting the size of the smallest inverter 41 to "1", the sizes of the inverters 38, 39, 40, 41 and 42 become "21.6", "10.8", "5.4", "1" and "1.6", respectively. Accordingly, the total of the inverter sizes shown in FIG. 5 becomes "40.4". In other words, the conventional clock driver circuit shown in FIG. 5 is disadvantageous in that the device size becomes large.
Furthermore, the conventional driver circuit shown in FIG. 6 is in common to the conventional driver circuit shown in FIG. 5 in which a pair of complementary output signals can be obtained from the non-inverted signal output terminal 3 and the inverted signal output terminal 2. However, since the conventional driver circuit shown in FIG. 6 includes the source follower circuit composed of the transistors 45 and 46 and the source follower circuit composed of the transistors 47 and 48, when any one of the transistors 45 and 48 acting as an active load is in a conductive condition, if the corresponding transistor 46 or 47 is turned on, a through current flows to pass from a high voltage VDD through the transistors 45 and the transistor 46 to ground GND, or from the high voltage VDD through the transistors 47 and the transistor 48 to the ground GND.